Long Term Evolution (LTE) is an evolution of the Third Generation Mobile Communication (3G). It improves and enhances the radio interface technologies of 3G, and uses Orthogonal Frequency Division Multiplexing (OFDM) and Multiple-Input Multiple-Output (MEMO) as sole standards of the wireless network evolution. LTE can provide 150 Mbit/s peak rate of uplink and 300 Mbit/s peak rate of downlink in 20 MHZ spectral bandwidth. Meanwhile, LTE improves the performance to cell-edge users, increases cell capacity and decreases system delay. Compared with 3G, LTE has advantages of high communication rate and spectrum efficiency, low wireless network delay, continuous area coverage and downward compatibility. However, the implementation of LTE requires a high-level design for User Equipment (UE) terminal, such as high baseband chip's ability to demodulate service data carried in a downlink channel and decode the demodulated data at a terminal, and taking as little as possible memory space of the baseband chip.
FIG. 1 illustrates a conventional method for processing a Physical Downlink Control Channel (PDSCH) in a TD-LIE system. Referring to FIG. 1, after a UE receives OFDM symbols sent from a base station, a Fast Fourier Transformation (FFT) processor 11 processes the received OFDM symbols to form FFT data. The FFT data is stored in a FFT buffer 12 and de-multiplexed by a Resource Element (RE) de-multiplexer 13, namely, extracting RE data in the PDSCH of the UE among the FFT data. Meanwhile, channel parameters are extracted from the FFT data through a Channel Estimation (CHE) unit 14, therefore a CUE result (i.e. channel parameters) which matches with an OFDM symbol is output into a CHE buffer 15. Then, after a MIMO demodulator 16 demodulates the RE data from the RE de-multiplexer 13 by employing the CHE results in the CHE buffer 15, the demodulated data (generally being soft-bit data) is stored in a buffer space 17 in the PDSCH. When the demodulated data in the buffer space 17 in the PDSCH accumulates to a subframe, a Forward Error Correction (FEC) decoder 18 starts to decode the subframe. And the FEC decoder 18 includes a de-scramble unit 181, a de-rate matching unit 182, a Hybrid Automatic Repeat Request (HARQ) unit 183, a channel decoding unit 184 and a check code decoding unit 185, etc.
Therefore, FEC decoding of the PDSCH is performed in subframe. In practice, a pipeline in subframe is formed between the MIMO demodulator 16 and the FEC decoder 18, namely, MIMO demodulation of a current subframe and FEC decoding of a previous subframe are performed in parallel. Therefore, soft-bit data of two subframes need to be cached in the buffer space 17 of the PDSCH, which occupies a lot of memory space of a baseband chip.
More information relative to a method for demodulating and decoding of a PDSCH may refer to US patent publication No. US2011085458A1 entitled “DOWNLINK CONTROL INFORMATION FOR EFFICIENT DECODING”, however, which still leaves aforementioned problems unsolved.